Logical Verification Engineer

Place：

Shanghai, Wuhan

Responsibility：

1、According to the design specification, extract function point、design test cases and coding;
2、Participate in the test platform design and redact;
3、Responsible for system simulation of the chip, submit Bug and responsible for tracking and regression, participate in the chip of the upper debugging;
4、Write simulation test plan and fill in the simulation test record.

Requirement：

1、Communications, electronics or related major;
2、Master the FPGA development related design process;
3、Master System Verilog language, can use common simulation tools and testing instruments;
4、Good software programming basis, strong ability of design and debugging.